1. Field
This disclosure relates generally to semiconductors, and more specifically, to digital logic circuitry.
2. Related Art
Digital circuits within integrated circuits are commonly designed using a standard cell design procedure. Circuits having predefined functions are referred to as cells and are arranged to form a desired global function. Standard cell designs achieve high integration and functionality and are therefore used for designing a system on chip (SOC). In the design process a functional block diagram is generated. A detailed functional description is generated using a hardware description language. The detailed functional description undergoes functional testing with a functional simulator. For logic design, the functional block diagram and the detailed functional description are converted to specific hardware to generate a logic diagram (netlist). Layout is performed where a circuit diagram is generated until a level enabling pattern of the logic expressed in the netlist is generated. A mask is then generated to wire and connect devices of the circuit diagram on the semiconductor substrate.
In a physical semiconductor device formed by this process, digital circuits such as flip-flops do not function accurately unless a setup time and a hold time are satisfactory. A setup time is the time required to present a data signal and maintain it before another signal is presented, and a hold time is an amount of time for which a data signal must be held after a clock signal changes. On-Chip Variation (OCV) can cause random or systematic variation in clock signal delays across an SOC. Various clock signal delays are caused by conductor or wire characteristics, such as resistance, capacitance, process, voltage and temperature variation. Signal delays also occur when a signal passes through a logic gate. When a data delay or clock delay occurs due to these natural characteristics, normal synchronous operations of flip-flops are affected and timing violations may occur, such as setup time violations and data hold violations.
In conventional circuit design processes, wire delays that may occur are predicted after layout. Then, timing analysis is performed based on the predicted wire delay, to determine where timing violations may occur so that changes may be made to the circuit to satisfy the required timing. Existing circuits which address flip-flop hold timing do so with the tradeoff of adding a significant amount of circuitry which is undesirable. The additional circuitry which functions to address setup and hold timing constraints also increases power consumption to an amount that is very undesirable for integrated circuits used in power-aware applications.